On Early X86-32 Processors

A memory controller, also known as memory chip controller (MCC) or a memory controller unit (MCU), is a digital circuit that manages the move of knowledge going to and from a pc's principal memory. When a memory controller is integrated into one other chip, similar to an integral a part of a microprocessor, it is often referred to as an built-in memory controller (IMC). Memory controllers include the logic essential to learn and write to dynamic random-entry memory (DRAM), and to supply the important memory refresh and different features. Reading and writing to DRAM is performed by selecting the row and column knowledge addresses of the DRAM as the inputs to the multiplexer circuit, the place the demultiplexer on the DRAM uses the converted inputs to select the correct memory location and return the info, which is then handed back by means of a multiplexer to consolidate the data so as to cut back the required bus width for the operation. Memory controllers' bus widths range from 8-bit in earlier programs, to 512-bit in more sophisticated techniques, where they're sometimes carried out as four 64-bit simultaneous memory controllers operating in parallel, although some operate with two 64-bit memory controllers getting used to entry a 128-bit memory system.



Some memory controllers, such as the one integrated into PowerQUICC II processors, include error detection and correction hardware. Many fashionable processors are additionally integrated Memory Wave Workshop management unit (MMU), which in many operating techniques implements virtual addressing. On early x86-32 processors, the MMU is built-in within the CPU, however the memory controller is often part of northbridge. Older Intel and PowerPC-primarily based computer systems have memory controller chips which might be separate from the principle processor. Often these are built-in into the northbridge of the computer, additionally typically known as a memory controller hub. Most trendy desktop or workstation microprocessors use an integrated memory controller (IMC), together with microprocessors from Intel, AMD, and people built across the ARM structure. Previous to K8 (circa 2003), AMD microprocessors had a memory controller carried out on their motherboard's northbridge. In K8 and later, AMD employed an integrated memory controller. Likewise, until Nehalem (circa 2008), Intel microprocessors used memory controllers applied on the motherboard's northbridge.



Nehalem and later switched to an built-in memory controller. Different examples of microprocessor architectures that use built-in memory controllers embody NVIDIA's Fermi, IBM's POWER5, and Solar Microsystems's UltraSPARC T1. Whereas an built-in memory controller has the potential to increase the system's performance, similar to by reducing memory latency, it locks the microprocessor to a selected type (or varieties) of memory, forcing a redesign in an effort to assist newer memory applied sciences. When DDR2 SDRAM was introduced, AMD released new Athlon 64 CPUs. These new models, with a DDR2 controller, use a special physical socket (generally known as Socket AM2), so that they'll solely fit in motherboards designed for the brand new sort of RAM. When the memory controller will not be on-die, the identical CPU may be installed on a brand new motherboard, with an up to date northbridge to make use of newer memory. Some microprocessors in the 1990s, such as the DEC Alpha 21066 and HP PA-7300LC, had integrated memory controllers; however, quite than for performance positive aspects, this was implemented to scale back the price of techniques by eliminating the necessity for an exterior memory controller.



Some CPUs are designed to have their memory controllers as dedicated exterior components that are not part of the chipset. An instance is IBM POWER8, which uses exterior Centaur chips that are mounted onto DIMM modules and act as memory buffers, L4 cache chips, and as the actual memory controllers. The primary version of the Centaur chip used DDR3 memory but an up to date version was later launched which may use DDR4. A number of experimental Memory Wave controllers comprise a second degree of tackle translation, along with the first level of tackle translation performed by the CPU's memory management unit to enhance cache and bus efficiency. Memory controllers integrated into certain Intel Core processors present memory scrambling as a function that turns user information written to the principle memory into pseudo-random patterns. Memory scrambling has the potential to forestall forensic and reverse-engineering analysis primarily based on DRAM knowledge remanence by effectively rendering varied sorts of chilly boot assaults ineffective.



In present observe, this has not been achieved; memory scrambling has solely been designed to handle DRAM-associated electrical issues. The late 2010s Memory Wave scrambling standards do address security points and aren't cryptographically secure or open to public revision or analysis. ASUS and Intel have their separate memory scrambling standards. ASUS motherboards have allowed the user to decide on which memory scrambling commonplace to use (ASUS or Intel) or whether or not to turn the characteristic off entirely. Double knowledge fee (DDR) memory controllers are used to drive DDR SDRAM, the place data is transferred on each rising and falling edges of the system's memory clock. Multichannel memory controllers are memory controllers the place the DRAM gadgets are separated onto a number of buses to permit the memory controller(s) to access them in parallel. This increases the theoretical quantity of bandwidth of the bus by an element of the variety of channels. While a channel for each DRAM would be the best resolution, including extra channels increases complexity and cost.